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OKI Semiconductor ML9055A-02
LCD Controller/Driver
PEDL9055A-02-01
Issue Date: Jul. 26, 2002
Preliminary
GENERAL DESCRIPTION
The ML9055A-02 is an LSI providing the bit map display on a dot matrix graphic LCD panel . With one chip, it is possible to construct a graphic display system with a maximum of 128 x 128 dots. Since all the functions necessary for driving the bit map type LCD panel are incorporated into a single chip, the ML9055A-02 allows to implement a dot matrix graphic LCD display system of bit map type with only a few chips in combination with an 8-bit microcomputer. Using the CMOS process and a built-in RAM, the ML9055A-02 is highly suitable for displays in battery-operated portable equipment.
FEATURES
* * * * * * * * * * * * * * * * Liquid Crystal Display (LCD) controller and driver Maximum display size: 128 columns x 128 rows Logic voltage: 1.8 to 3.0 V LCD drive voltage: 4.0 to 16.0 V Serial interface (3-line or 4-line, write only) and parallel interface Built-in voltage multiplier and oscillator circuit for display timing control LCD drive bias: 1/5 to 1/12 Duty ratio: 1/16 to 1/128 Voltage regulator temperature coefficient: -0.125%/ oC Voltage multiplier: x3, x4, x5, x6 Contrast adjustjment: 64 levels available 4-level gray scale Partial display function Scroll function Frame frequency: 180 Hz Package: Gold bump chip, TCP ML9055A-02DVWA (Gold bump chip name) ML9055A-02DVVAZ01L (General TCP name)
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BLOCK DIAGRAM
COM125 COM126 COM127
SEG125 SEG126 SEG127
...
COM0 COM1 COM2
SEG0 SEG1 SEG2
...
VDD V0 V1 V2 V3 V4 VSS
128-Segment Driver Circuit
128-Common Driver Circuit
Segment Controller
Common Controller
Voltage Follower Circuit
Oscillation Circuit/
Display Timing Control
TEST1
VR VEXT INTRS REF VOUT C1+ C1- C2+ C2- C3+ C4+ C5+ VCI
Voltage Regulator Circuit
Line Address Circuit
Display Data RAM Column Address Circuit
I/O Buffer
Page Address Circuit
Voltage Multiplier Circuit
Instruction Register Status Register
Microcomputer Interface Logic
RESET PS0 PS1 RS CS R/W (WR) E (RD) DB7 (SDATA) DB6 (SCLK) DB5 DB4 DB3 DB2 DB1 DB0
TEST2
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PIN CONFIGURATION (STANDARD TCP: BRONZE-FOIL FACE UP)
NC1 PS0 PS1 CS RESET RS R/W (WR) E (RD) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VCI VSS VOUT C5+ C3+ C1- C1+ C2+ C2- C4+ REF VEXT INTRS V4 V3 V2 V1 V0 VR TEST1 NC2
NC NC1 COM113 COM112 COM111 COM110
COM66 COM65 COM64 SEG127 SEG126
SEG2 SEG1 SEG0 COM14 COM15
COM60 COM61 COM62 COM63 NC NC2
Note 1: This drawing is not a true external view of TCP, but it primarily shows the TCP pin layout. Note 2: The TCP shown above is a standard TCP and does not have COM0 to COM13 pins and COM114 to COM127 pins. Also there is no TEST2 pin on the TCP. (In the TCP, 128 lines from SEG0 to SEG127 and 100 lines from COM14 to COM113 are derived as the output pins.) The external shape and the number of output pins of TCP can be customized as needed. Note 3: Do not connect the NC pins to outside or any other pins. NC stands for "No Connection". The NC pins are not connected to the chip. All NC pins are independent. NC1 remains connected to COM112 before dicing. Although the input side NC1 remains connected with the output side NC1 by dicing, the connection with COM112 is lost. Similarly, NC2 remains connected to COM63 before dicing. Although the input side NC2 remains connected with the output side NC2 by dicing, the connection with COM63 is lost.
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PIN DESCRIPTIONS
Function Symbol VDD VSS V0 V1 Power Supply V2 V3 V4 C1- C1+ C2- C2+ C3+ C4+ C5+ O O O O O O O Connection pins of capacitors for multiplied voltage Connect capacitors for the voltage multiplier to these pins. (Connect pins with + sign to positive polarity of respective capacitors and pins with - sign to negative polarity of respective capacitors.) The connections of capacitors for multiplying voltage differ depending upon the voltage multiplication. The connections of the capacitors for multiplying voltage are described in the "Voltage Multiplier" section. Voltage multiplier input/output pins When using an internal voltage multiplier, the following voltage is output from the VOUT pin: VOUT = VCI x Voltage multiplication When not using the internal voltage multiplier, input the external power supply voltage from this VOUT pin. About the pin processing in the case of an external input, refer to the "LCD Drive Power Supply Circuit" section. Multiplied voltage input pin of internal voltage multiplier When using an external power supply, tie this pin to VSS. V0 voltage adjustment pin (Adjusts V0 using external resistors.) When INTRS pin = "L", the V0 voltage is adjusted by connecting external resistors to this pin. The method of connecting external resistors is described in the "LCD Drive Power Supply Circuit" section. When INTRS pin = "H", keep this VR pin open. Note: When INTRS pin is "H", the internal resistors are selected for adjusting V0 and a very high internal resistor gets connected to VR pin. Therefore this ML9055A can be vulnerable to external noise. In designing the circuit board, pay proper attention to the external noise and leak. Internal/external reference voltage select pin. (L: External, H: Internal) External reference voltage (VREF) input pin. (Valid only when REF= L.) When using the internal reference power supply, keep this pin open. V0 adjustment resistor select pin (L: External, H: Internal) I/O Type Supply Supply Description Power supply Ground LCD drive power supply voltage pin V0, and LCD drive bias voltage pins V1 to V4 When applying the LCD drive power supply voltage and each LCD drive bias voltage from outside, notice to hold the following relationship: VSS < V4 < V3 < V2 < V1 < V0 The LCD drive bias voltages are generated when using the built-in voltage follower. For the value of each generated bias voltage, refer to the "Voltage Follower Circuit" section in this document.
VOUT
I/O
LCD Driver Supply
VCI
I
VR
I
REF VEXT INTRS
I I I
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Function
Symbol RESET
Type I
Description Reset input pin (active "L") Parallel/serial data setting (H = Parallel, L = Serial) PS0 L PS1 L H L H Interface 3-line serial interface 4-line serial interface 8080 parallel interface 6800 parallel interface
PS0 PS1
I
L H H
Microcomputer Interface
CS RS
I I
R/W (WR)
I
E (RD)
I
DB0 to DB7 SEG0 to SEG127 COM0 to COM127 TEST1 TEST2
I/O
Note: When using the serial interface, leave D0-D5 open and connect E (RD) and R/W (WR) to VDD or VSS. Chip select input pin (active "L") Register select input pin Distinguishes between display data (H) and command data (L). Connect this pin to VDD or VSS for 3-line serial interface. When connected to a 68-series MPU: Read/write execute control pin (H = read, L = write) When connected to an 80-series MPU: Write execute control pin (L = write) When connected to a 68-series MPU: E clock input pin When connected to an 80-series MPU: Read execute control pin (L = read) When parallel interface is selected, 8-bit data bus pin When serial interface is selected, DB0 to DB5: Open DB6(SCLK): Serial clock input DB7(SDATA): Serial data input LCD segment driver outputs LCD common driver outputs Test pin of this LSI. Connect this pin to VDD. Test pin of this LSI. Leave this pin open
O O I O
LCD Driver Test
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ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Power Supply Voltage Voltage Multiplier Input Voltage Voltage Multiplier Output Voltage LCD Drive Voltage LCD Drive Bias Voltage Logic Input Voltage Storage Temperature Range Symbol VDD VCI VOUT V0 Vm (*3) VI Tstg Condition Tj = 25C Tj = 25C Tj = 25C Tj = 25C Tj = 25C Tj = 25C Chip Rating -0.3 to +4.0 -0.3 to +4.0 (*1) -0.3 to +20.0 -0.3 to +20.0 (*2) -0.3 to V0 +0.3 (*4) -0.3 to VDD +0.3 -55 to +150 Unit V V V V V V C
*1. *2. *3. *4.
Notice that voltage multiplier output voltage VOUT should not exceed 20 V. V0 should not exceed VOUT. Vm indicates V1, V2, V3 and V4. Notice that Vm should not exceed 20 V.
(VSS = 0 V) Parameter Symbol VDD VCI VOUT V0 V1 V2 V3 V4 VEXT Tjop Condition -- -- -- -- -- -- -- -- -- Chip Range 1.8 to 3.0 VDD to 3.0 (*1) 5.4 to 16.0 4.0 to VOUT-1 3.2 to 14.7 (*2) 2.4 to 13.4 (*2) 1.6 to 2.7 (*2) 0.8 to 1.4 (*2) 1.8 to VDD -40 to +85 Unit V V V V V V V V V C
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage Voltage Multiplier Input Voltage Voltage Multiplier Output Voltage LCD Driver voltage LCD Driver Bias Voltage 1 LCD Driver Bias Voltage 2 LCD Driver Bias Voltage 3 LCD Driver Bias Voltage 4 External Reference Voltage Operating Temperature
*1. Notice that the voltage multiplier output voltage VOUT is 16 V or below. *2. Notice that VOUT>V0>V1>V2>V3>V4. Do not expose the ML9055A to light when in use.
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 1.8 to 3.0 V, VSS = 0 V, Tj = -40 to +85C) Parameter High Input Voltage Symbol VIH Condition -- Min. 0.8 x VDD Typ. -- Max. VDD Unit V Applied pins RESET, PS0, PS1, CS, RS, R/W (WR), E (RD), Low Input Voltage VIL -- 0.0 -- 0.2 x VDD DB7 (SDATA), V DB6 (SCLK), DB5-DB0, INTRS, REF High Output Voltage Low Output Voltage VOH VOL IOH = -0.5 mA IOL = 0.5 mA 0.8 x VDD 0.0 -- -- VDD 0.2 x VDD V V DB7 (SDATA), DB6 (SCLK), DB5-DB0 RESET, PS0, PS1, CS, RS, R/W (WR), E (RD), DB7 (SDATA), DB6 (SCLK), DB5-DB0, INTRS, REF SEG0-SEG127, COM0-COM127 V0 VOUT, V0
Input Current
IIL
VIN = VDD or VSS
-1.0
+1.0
A
LCD Driver On Resistance Internal resistance ratio error VOUT-V0 Voltage
RON Rratio VOT0
Tj = 25C, 1/8 bias V0 = 8 V -- V0 load current = 300 A VOUT = 8 V(applied externally) LCD output, no load
-- -- 1
2.5 -- --
5 3 --
k % V
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Parameter
Symbol
Condition Tj= 25 C, VDD = VCI = 2.75 V x5 voltage multiplier 1/100 duty Frame frequency: 180 Hz Display: Off (*1) Tj= 25oC, VDD = VCI = 2.75 V x5 voltage multiplier 1/128 duty Frame frequency: 220 Hz Display: Off (*1) Tj= 25oC,
o
Min.
Typ.
Max.
Unit
Applied pins
IDD11
--
150
230
A
IDD12
--
185
285
A
Operating Current Consumption IDD21
VDD = VCI = 2.75 V x5 voltage multiplier Display: On 1/100 duty Frame frequency: 180 Hz (Full checker board pattern (*1) Tj= 25oC, VDD = VCI = 2.75 V x5 voltage multiplier IDD22 Display: On 1/128 duty Frame frequency: 220 Hz (Full checker board pattern (*1) -- 370 530 A -- 300 430 A VDD, VCI (*2)
Current Consumption in Power Save Mode Voltage Multiplier Efficiency
ISLEEP
Power save mode Tj = 25C, VDD = 3.0 V x3/x4/x5/x6 Using internal power supply No load Tj = -20C
--
--
2
A
EVC
95
99
--
%
VOUT
-- 2.04 --
2.22 2.10 1.98
-- 2.16 --
V V V VEXT (*3)
Reference Voltage
VREF
Tj = 25C Tj = 70C
(*1) No CPU access state. No LCD panel load. Other conditions: 1/12 bias; contrast = 60; internal resistance ratio setting = 5.8; 3-FRC; 9-level PWM; frame inversion (*2) The current consumption is a sum of VDD current and VCI current. (*3) Vref voltage is measurable in the test mode, but cannot be measured when a customer is using the ML9055A in normal circumstances.
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AC Characteristics Serial Interface Timing
Parameter Serial Clock Frequency Serial Clock Cycle Time Serial Clock "H" Pulse Width Serial Clock "L" Pulse Width Data Setup Time Data Hold Time Chip Select Setup Time Chip Select Hold Time Chip Select "H" Pulse Width Register Select Setup Time(*1) Register Select Hold Time(*1) Input Signal Rise Time (*2) Input Signal Fall Time (*2) Symbol fCLK tCLK tWHS tWLS tDS tDH tCSS tCSH tCH tRSS tRSH tr tf Min. -- 111 50 50 50 50 60 50 50 60 60 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- (VDD = 1.8 V, Tj = -40 to +85C) Max. Unit 9 MHz -- ns -- ns -- ns -- ns -- ns -- ns -- ns -- ns -- ns -- ns 15 ns 15 ns
(Note) (*1) Not applied to 3-line serial interface. (*2) Applied to all input pins.
Parameter Serial Clock Frequency Serial Clock Cycle Time Serial Clock "H" Pulse Width Serial Clock "L" Pulse Width Data Setup Time Data Hold Time Chip Select Setup Time Chip Select Hold Time Chip Select "H" Pulse Width Register Select Setup Time(*1) Register Select Hold Time(*1) Input Signal Rise Time (*2) Input Signal Fall Time (*2) Symbol fCLK tCLK tWHS tWLS tDS tDH tCSS tCSH tCH tRSS tRSH tr tf Min. -- 58.8 25 25 25 25 30 25 30 30 30 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- (VDD = 2.7 V, Tj = -40 to +85C) Max. Unit 17 MHz -- ns -- ns -- ns -- ns -- ns -- ns -- ns -- ns -- ns -- ns 15 ns 15 ns
(Note) (*1) Not applied to 3-line serial interface. (*2) Applied to all input pins.
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Parallel Interface Timing (68-series MPU)
Parameter Address Setup Time Address Hold Time CS "L" Pulse Width for Write CS "H" Pulse Width for Write CS "L" Pulse Width for Read CS "H" Pulse Width for Read E "H" Pulse Width for Write E "L" Pulse Width for Write E "H" Pulse Width for Read E "L" Pulse Width for Read Data Setup Time Data Hold Time during Write Data Access Time Data Hold Time during Read System Write Cycle Time System Read Cycle Time Input Signal Rise Time (*1) Input Signal Fall Time (*1) Symbol tAS tAH tCSL tCSH tCSL tCSH tEH tEL tEH tEL tDS tDH tACC tOH tCYC tCYC tr tf Condition -- -- -- -- -- -- -- -- -- -- -- -- CL = 100 pF -- -- -- -- -- Min. 0 0 60 60 100 100 60 60 100 100 40 10 -- 10 150 330 -- -- (VDD = 1.8 V, Tj = -40 to +85C) Typ. Max. Unit -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- 90 ns -- 90 ns -- -- ns -- -- ns -- 15 ns -- 15 ns
(Note) (*1) Applied to all input pins.
Parameter Address Setup Time Address Hold Time CS "L" Pulse Width for Write CS "H" Pulse Width for Write CS "L" Pulse Width for Read CS "H" Pulse Width for Read E "H" Pulse Width for Write E "L" Pulse Width for Write E "H" Pulse Width for Read E "L" Pulse Width for Read Data Setup Time Data Hold Time during Write Data Access Time Data Hold Time during Read System Write Cycle Time System Read Cycle Time Input Signal Rise Time (*1) Input Signal Fall Time (*1) Symbol tAS tAH tCSL tCSH tCSL tCSH tEH tEL tEH tEL tDS tDH tACC tOH tCYC tCYC tr tf Condition -- -- -- -- -- -- -- -- -- -- -- -- CL = 100 pF -- -- -- -- -- Min. 0 0 40 40 60 60 40 40 60 60 30 5 -- 10 150 166 -- -- (VDD = 2.7 V, Tj = -40 to +85C) Typ. Max. Unit -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- 50 ns -- 50 ns -- -- ns -- -- ns -- 15 ns -- 15 ns
(Note) (*1) Applied to all input pins.
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Parallel Interface Timing (80-series MPU)
Parameter Address Setup Time Address Hold Time CS, WR "L" Pulse Width for Write CS, WR "H" Pulse Width for Write CS, RD "L" Pulse Width for Read CS, RD "H" Pulse Width for Read Data Setup Time Data Hold Time during Write Data Access Time Data Hold Time during Read System Write Cycle Time System Read Cycle Time Input Signal Rise Time (*1) Input Signal Fall Time (*1) Symbol tAS tAH tCSL tCSH tCSL tCSH tDS tDH tACC tOH tCYC tCYC tr tf Condition -- -- -- -- -- -- -- -- CL = 100 pF -- -- -- -- -- Min. 0 0 60 60 100 100 40 10 -- 10 150 330 -- -- (VDD = 1.8 V, Tj = -40 to +85C) Typ. Max. Unit -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- 90 ns -- 90 ns -- -- ns -- -- ns -- 15 ns -- 15 ns
(Note) (*1) Applied to all input pins.
Parameter Address Setup Time Address Hold Time CS, WR "L" Pulse Width for Write CS, WR "H" Pulse Width for Write CS, RD "L" Pulse Width for Read CS, RD "H" Pulse Width for Read Data Setup Time Data Hold Time during Write Data Access Time Data Hold Time during Read System Write Cycle Time System Read Cycle Time Input Signal Rise Time (*1) Input Signal Fall Time (*1) Symbol tAS tAH tCSL tCSH tCSL tCSH tDS tDH tACC tOH tCYC tCYC tr tf Condition -- -- -- -- -- -- -- -- CL = 100 pF -- -- -- -- -- Min. 0 0 40 40 60 60 30 5 -- 10 150 166 -- -- (VDD = 2.7 V, Tj = -40 to +85C) Typ. Max. Unit -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- -- ns -- 50 ns -- 50 ns -- -- ns -- -- ns -- 15 ns -- 15 ns
(Note) (*1) Applied to all input pins.
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OSC Frequency
(VDD = 1.8 to 3.0 V, Tj = 25C) Parameter Frame Frequency Symbol fFR Condition 9PWM, 1/100 duty 9PWM, 1/128 duty Min. 150 180 Typ. 180 220 Max. 210 260 Unit Hz Hz
Reset Timing
(VDD = 1.8 to 3.0 V, Tj = -40 to +85C) Parameter Reset Pulse Width Input Signal Rise Time Input Signal Fall Time Symbol tRES tr tf Condition -- -- -- Min. 1.5 -- -- Typ. -- -- -- Max. -- 15 15 Unit s ns ns
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TIMING DIAGRAMS
3- and 4-Line Serial Interface Timing Diagram
tCH
VIH VIL VIL
CS
tCSS tCLK
0.9VDD
tr tWLS tWHS
0.9VDD 0.1VDD 0.1VDD
tf
tCSH
0.9VDD
0.9VDD 0.1VDD
SCLK
0.1VDD
0.1VDD
tDS
tDH
VIH VIL
SDATA
DB7
VIH DB6 VIL
DB1
DB0
tRSS tRSH
VIH VIL
DB7
RS
VIH VIL
VIH = 0.8VDD VIL = 0.2VDD
In 3-line system, the ML9055A interfaces with a microcomputer by 3 lines namely, CS, SCLK, and SDATA. The method to switch between the data and command in the 3-line system is described in the "Microcomputer Interface" section of Functional Description. In 4-line system, the ML9055A interfaces with a microcomputer by 4 lines namely CS, SCLK, SDATA, and RS. If CS holds "L", the display data and command write operations can be executed consecutively. At this time, the chip select setup time, tCSS, stipulates the time up to the first falling edge of SCLK after the falling edge of CS. And the chip select hold time, tCSH, stipulates the time from the rising edge of the last SCLK up to the rising edge of CS.
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Parallel Interface Timing Diagram for 68-Series MPU
RS, R/W
VIH VIL
VIH VIL
tAS tCSL
tAH tCSH
0.9VDD 0.1VDD 0.1VDD 0.9VDD
0.9VDD
CS
tCYC tr E
0.9VDD 0.1VDD
tEH
tf
0.9VDD 0.1VDD
tEL
tDS
VIH VIL
tDH
VIH VIL
0.1VDD
DB7-DB0 (Write) tACC DB7-DB0 (Read)
tOH
VOH VOL VOH VOL
VIH = 0.8VDD VIL = 0.2VDD VOH = 0.8VDD VOL = 0.2VDD
Note 1: The trace impedance (specially, the VDD, VSS, VCI impedance and the data bus trace capacitance etc,) between this chip and circuit board should be designed as low as possible. Factors such as not sufficiently low trace impedance, LCD panel of large size, and high trace impedance of the microcomputer interface, would become a cause of the ML9055A malfunction. In such a situation, use the microcomputer interface not for reading, but for writing only to reduce the power supply noise. Note 2: The system cycle time tCYC at write and at read is different in the ML9055A. Please keep to the system write time cycle when switching from the write operation to the read operation and, similarly, keep to the system read time cycle when switching from the read operation to the write operation. Note 3: The overlapping duration when CS is "L" and E is "H" must satisfy tCSL or tEH. Reference points tAS and tACC in this case are decided by CS or E, whichever is slower, and the reference points tAH, tDS, TDH and tOH are decided by CS or E, whichever is faster.
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Parallel Interface Timing Diagram for 80-Series MPU
VIH VIL VIH VIL
RS
tAS tf
0.9VDD
tAH tCSL tr tCSH
0.9VDD 0.9VDD
CS, RD WR
0.1VDD
tCYC tDS
0.1VDD
tDH
DB7-DB0 (Write) tACC DB7-DB0 (READ)
VIH VIL
VIH VIL
tOH
VOH VOL VOH VOL
VIH = 0.8VDD VIL = 0.2VDD VOH = 0.8VDD VOL = 0.2VDD
Note 1: The trace impedance (specially, the VDD, VSS, VCI impedance and the data bus trace capacitance etc.,) between this chip and circuit board should be designed as low as possible. Factors such as not sufficiently low trace impedance, LCD panel of large size, and high trace impedance of the microcomputer interface, would become a cause of the ML9055A malfunction. In such a situation, use the microcomputer interface not for reading, but for writing only to reduce the power supply noise. Note 2: The system cycle time tCYC at write and at read is different in the ML9055A. Please keep to the system write time cycle when switching from the write operation to the read operation and, similarly, keep to the system read time cycle when switching from the read operation to the write operation.
Reset Timing
tf tRES RESET 0.9 VDD 0.9 VDD 0.1 VDD 0.1 VDD tr
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FUNCTIONAL DESCRIPTION
Microcomputer Interface * Serial Interface
The ML9055A communicates with a microcomputer via clock-synchronized serial interface when PS0 holds "L". Read operation is inhibited in the serial interface. Write operation is executed only when CS is low. Data should be input from the most signification bit (MSB). The data latches to the internal shift registers on the rising edge of the serial clock SCLK, and then processed as 8-bit data on the rising edge of the 8th clock. When display data is written to the RAM, the column address is incremented automatically by one only. If CS holds "L", the serial data can be input continuously. If CS goes "H" before 8 serial clocks are sent while the serial data is being input, the discontinued bytes become an invalid data, but the data transmitted prior to that is valid. The serial interface includes a 3-line serial interface and a 4-line serial interface. When PS1 is "L", the 3-line serial interface is selected. The 3-line serial interface is composed of serial data (SDATA), serial clock (SCLK), and chip select (CS). The set display data length command identifies whether the data from a microcomputer is a display data or a command data. The specified number of bytes (1 to 256) in data that follow the set display data length command is processed as the display data. And the next byte, after sending the number of display data bytes specified by the set display data length command, is processed as the command data. If CS goes "H" while the number of bytes of serial data specified by the set display data length command is being input, the discontinued bytes become an invalid data. And the bytes sent prior to the transmitted data is a valid data. The next input data will be processed as the command data. When PS1 is "H", the 4-line serial interface is selected. The 4-line serial interface is composed of serial data (SDATA), serial clock (SCLK), chip select (CS), and register select (RS). The register select pin RS is used to differentiate whether the data sent from a microcomputer is a display data or a command data. At RS pin = "H", the input data is a display data. And at RS pin = "L", the input data is a command data. Note: Do not use the ML9055A with CS tied to "L". Make sure to return the CS to "H" at the end of a command or data input. However, use the ML9055A with CS at "L" when the set display data length command only is input, including the input data, at the end of this command. Return the CS to "H" at the end of all data input.
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* Parallel Interface The ML9055A communicates with a microcomputer via the parallel interface when the PS0 is "H". The ML9055A includes a parallel interface for 68-series MPU and a parallel interface for 80-series MPU. When both PS0 and PS1 are "H", the interface is an 8-bit parallel interface for 68-series MPU. Both read and write operations are performed only when the Chip Select (CS) pin is "L"and E clock (E) pin is "H". The Register Select (RS) pin is used to discriminate whether the data accessed from a microcomputer is a display data or a command data. When the RS pin is "H", the accessed data is a display data. And when the RS pin is "L", the accessed data is a command data. Table 1-1. Parallel Interface Function (68-series MPU)
(x Don't care) E clock (E) H H H H L x Register Select (RS) L L H H x x Chip Select (CS) L L L L x H Read/Write (R/W) L H L H x x Operation Write command data. Read status register. Write display data. Read display data. Invalid Invalid
When PS0 is "H" and PS1 is "L", the interface is an 8-bit parallel interface for 80-series MPU. Both read and write operations are performed only when the Chip Select (CS) is "L". The Register Select (RS) pin is used to discriminate whether the data accessed from a microcomputer is a display data or a command data. When the RS pin is "H", the accessed data is a display data. And when the RS pin is "L", the accessed data is a command data. Table 1-2. Parallel Interface Function (80-series MPU)
(x Don't care) Chip Select (CS) L L L L L H Register Select (RS) L L H H x x Write (WR) L H L H H x Read (RD) H L H L H x Operation Write command data. Read status register. Write display data. Write display data. Invalid Invalid
Note: Do not simultaneously input "L" to WR and RD to avoid the ML9055A malfunction.
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LCD Drive Power Supply Circuit The LCD drive power supply circuit composed of a voltage multiplier (VC), a voltage regulator (VR), and a voltage follower (VF) is controlled by the set power supply configuration instruction. Table 2. Power Supply Circuit Configuration
Power supply configuration
(Note 1)
LCD drive power supply circuit VC ON OFF OFF OFF VR ON ON OFF OFF VF ON ON ON OFF VOUT Output
Pin state (Note 2) V0 Output Output External input External input V1 - V4 Output Output Output External input
Configuration All internal LCD drive power supply circuits used Voltage regulator and voltage follower used Voltage follower only used External power supply used
(VC VR VF) 111 011 001 000
External input Shorted with V0 Shorted with V0
Note 1: Although the set power supply configuration instruction allows to input commands to perform settings also of combinations other than shown in Table 2, do not perform such settings as would cause the ML9055A malfunction. Note 2: When the pin state is "output", connect the specified capacitors to VOUT, V0 and V1 to V4. * Voltage multiplier
The voltage multiplier is used to increase the VCI voltage applied to VCI pin up to the set multiple value. The setting enable voltage multiples are x3, x4, x5, and x6. These multiples are set by the voltage multiplication instruction. After voltage multiplication, the voltage is output from VOUT pin, which is used as a power supply for the voltage regulator and voltage follower. A voltage multiplier is configured in conjunction with external capacitors. As shown in Figure 1, to configure x3 to x6 multiplications, connect appropriate capacitors to the chip externally. Connect the capacitors to configure a voltage multiplier with the maximum multiplication used. Do not set the voltage multiplication by a command larger than the enable setting by the external capacitors because it would become a cause of the ML9055 unstable operation. Note: Use the voltage multiplier output voltage VOUT, and the LCD drive voltage V0, at the recommended operating voltage 16.0 V or below.
x4 voltage multiplication
- + Vss VOUT C5+ C3+ - + + - C1- C1+ C2+ C2- C4+ + - - + + - - +
x3 voltage multiplication
Vss VOUT C5+ C3+ C1- C1+ C2+ C2- C4+
x5 voltage multiplication
Vss VOUT C5+ C3+ C1- C1+ C2+ C2- C4+ + - - + + - - + - +
x6 voltage multiplication
Vss VOUT C5+ C3+ C1- C1+ C2+ C2- C4+ + - - + + - - + - + + -
Figure 1. Voltage Multiplier Setting (C = 0.8 F to 5.7 F)
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* Voltage Regulator Circuit
VEXT
Internal reference voltage circuit
VREF VCON +
VOUT Electroni c volume circuit
Switching by REF pin setting
-
V0 Rb VR Ra VSS
Figure 2. Voltage Regulator Circuit
The voltage regulator is composed of an internal reference voltage circuit, an electronic volume circuit, and an amplifier circuit. The internal reference voltage circuit outputs the reference voltage, VREF = 2.1 V (Tj = 25oC). This reference voltage VREF has a temperature co-efficient of 0.125%/oC. The reference voltage VREF is input to the electronic volume circuit. VREF can be input from VEXT pin also by the set REF pin instruction. (Refer to Table 3.) Table 3. V REF Voltage at Tj = 25C
REF L H Temp. coefficient (Depends on externally connected power supply.) -0.125%/C V REF (V) VEXT pin value 2.1 V
The electronic volume circuit converts the input reference voltage, VREF, to the contrast control voltage, Vcon, expressed by the following equation: VCON = (1- (63 - a)/210) x VREF Here, parameter "a" is the contrast setting value shown in Table 4. (Levels 0 to 63 can be set.)
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Table 4. Contrast Setting Value
C5 0 0 0 0 0 Contrast setting value C4 C3 C2 C1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 : 1 1 1 1 1 1 1 1 1 1 C0 0 1 0 1 0 0 1 Parameter a 0 1 2 3 4 : 62 63
The contrast control voltage Vcon, that is output from the electronic volume circuit, is input to the amplifier circuit and amplified to the LCD drive voltage V0, expressed by the following equation by the ratio of resistor Ra to Rb. V0 = (1 + Rb/Ra) x VCON Resistor Ra and resistor Rb can select either internal or external resistor by INTRS pin setting. * Internal Resistor Configuration When "H" is input to INTRS pin, resistor Ra and resistor Rb in the IC are selected. The resistance ratio Rb/Ra is determined by the set internal resistance ratio command. Table 5 shows amplification factor of the amplifier circuit. Figure 3 shows the variable range of LCD drive voltage V0 at Tj = 25oC when using the internal resistors.
Table 5. Internal Resistance Ratio Setting
Internal resistance ratio setting value R2 R1 R0 000 001 010 011 100 101 110 111 Amplification factor 1 + Rb/Ra 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2
*
External Resistor Configuration
When "L" is input to the INTRS pin, the internal resistors are separated and the externally connected resistors Ra and Rb set the amplification factor. Similar to Figure 2, connect an external resistor Ra across VR and VSS pins, and an external resistor Rb across VR and V0 pins. Note: The sum of the externally connected resistors Ra and Rb should be in the 500 k to 5 M range.
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16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0
Internal Resistance Ratio Setting Value (R2 R1 R0) 111 110 101 100 011
V0 Voltage (V)
010 001 000
0
7
15
23
31 Contrast Setting Tj = 25C
39
47
55
63
Figure 3. V0 Variable Range When Using Internal Reference Voltage and Internal Resistors
* Voltage Follower Circuit With LCD drive voltage V0 as a reference voltage, 4 LCD drive bias voltages are generated. The LCD bias is determined by the set LCD bias ratio command. The available bias levels are: 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, and 1/12. Connect capacitors of 0.376 F to 2.4 F to the voltage follower outputs for stabilizing the voltage. To determine optimal bias setting: Let the display duty be 1/D, then the optimal bias ratio is 1/(1 +
D ).
Table 6. LCD Drive Voltage Levels vs. Bias
LCD drive bias ratio 1/n V1 (n-1)/n x V0 V2 (n-2)/n x V0 V3 2/n x V0 V4 1/n x V0
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*
Power Supply Configuration Examples
VDD VDD VDD
INTRS VCI VEXT VOUT C5+ C4+ C3+ C2+ C2- C1+ C1- VR V0 V1 V2 V3 V4
REF
INTRS VCI VEXT VOUT C5+ C4+ C3+ C2+ C2- C1+ C1- VR V0 V1 V2 V3 V4
REF
Vss
INTRS VCI VEXT
REF
Vss
C2
Capacitors for multiplying voltage
C2
Capacitors for multiplying voltage
Ra Rb C1 C1 C1 C1 C1
External power supply
VOUT C5+ C4+ C3+ C2+ C2- C1+ C1- VR C1 C1 C1 C1 C1 V0 V1 V2 V3 V4
C1 C1 C1 C1 C1
(a) Using all internal power supplies and internal resistors
VDD
(b) Using all internal power supplies and external resistors
VDD
(c) Using all external reference power supply, voltage follower, and internal resistors
VDD
Vss
External power supply
External VEXT Power Supply VOUT C5+ C4+ C3+ C2+ C2- C1+ C1- VR C1 C1 C1 C1 C1 V0 V1 V2 V3 V4
INTRS VCI
REF Vss
INTRS VCI VEXT VOUT C5+ C4+ C3+ C2+ C2- C1+ C1- VR V0 V1 V2 V3 V4
REF Vss
INTRS VCI VEXT VOUT C5+ C4+ C3+ C2+ C2- C1+ C1- VR V0
REF
External power supply
C1 C1 C1 C1
External power supply
V1 V2 V3 V4
(d) Using voltage regulator, voltage follower, and internal resistors
(e) Using voltage follower
(f) Using external power supply only
Figure 4. Power Supply Configuration Examples Note 1: The bias capacitor C1 connected to the LCD drive bias pin should be in the 0.376 F to 2.4 F range. And the capacitors for multiplying voltage connected to the connect pins for these capacitors, and stabilizing capacitor C2 connected to the voltage multiplier input/output pin VOUT should be in the 0.8 F to 5.7 F range. Note 2: In the case of using an external power supply, apply VSS to pin VCI. And when not using an external reference voltage, keep the pin VEXT open.
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Partial Display Function The set display lines count instruction allows the display duty to be set to any value from 1/16 duty to 1/128 duty line-by-line, and also allows the display duty to be set according to the used panel. Also, the partial display function can display a part of the common lines only on the used LCD panel out of the total common lines, and accordingly sets the supply voltages, bias ratio and voltage multiplication thus reducing the current consumption. The method of changing the number of display lines is described in the "Partial Display Change Sequence" section of the OPERATING SEQUENCE. Display Data RAM For performing the bit-map display in the ML9055A, the data RAM is arranged into 2-dimensional 128 rows x 128 columns corresponding to the display image, and a specific element is specified by the row address (0 to 127) and column address (0 to 127). Each element stores a 2-bit data that indicates the level of gradation i.e., gray scale, of a pixel corresponding to an element. (Refer to Figure 5.) The relationship between COM output numbers and RAM row addresses can be reversed by the set COM scan direction command. The relationship between SEG output numbers and RAM column addresses can be reversed by the ADC select command. This enhances the freedom in relationship between the panel and chip location at the time of implementation. Moreover, it is possible to provide an offset to the row addresses and COM numbers by the set scanning start COM command allowing to scroll a display in the common direction. (Refer to Figure 6.) Since the microcomputer interface data is in bytes, the data for 8 pixels of 8 rows x 1 column is collectively handled as 1 byte. For this reason, the RAM read/write location is specified by the upper 4 bits of a row address (called a page address) and a column address. In byte, the larger row address side is positioned to the upper bit side. Since 1 pixel data consists of 2 bits, the read/write operations are performed in the order of upper/lower bits by accessing 2 times consecutively. As for the access procedure, the page address and column address are first set by command followed by the execution of display data read/write commands. It is not necessary to set again the column address when reading/writing the display data on the same page in the order of column address by the column address automatic increment function. Meanwhile, when reading, it is necessary to read a dummy display data once between the address setting and display data reading. For additional details, refer to the Display Data Write Sequence, Display Data Read Sequence, and Read Modify Write Sequence in the OPERATING SEQUENCE section.
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Data Bus Weight Page Address D3 D2 D1 D0
First Byte
Second Byte
Line Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
COM Outputs
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
0
0
0
0
0
0
0
1
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
1
1
1
0
1
1
1
1
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEG124 03 7C SEG125 02 7D SEG126 01 7E SEG127 00 7F SEG0 7F 00 SEG1 7E 01 SEG2 7D 02 SEG3 7C 03
70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127
S0 bit of ADC = 0 S0 bit of ADC = 1
Row Address (Mapping depends on COM scan direction setting) Column Address
Figure 5. Display Data RAM Map
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RAM row address R0
COM output COM0
RAM row address R0
COM output COM0
COMj Rk Rk COM128-j-D
COMj+ D-1 Rk+D-1 Rk+D-1 COM127-j
R127
COM127
R127
COM127
(a) COM scan direction SC0 = 0 Scan start COM setting = j Display start row address setting = k Display line count setting = D RAM row address R0 COM output COM0
(b) COM scan direction SC0 = 1 Scan start COM setting = j Display start row address setting = k Display line count setting = D RAM row address R0 COM output COM0
R(k+D-1) -128
COMj
R(k+D-1) -128 COM128-j-D
COMj+ D-1 COM127-j Rk R127 COM127 Rk R127 COM127
(c) COM scan direction SC0 = 0 Scan start COM setting = j Display start row address setting = k Display line count setting = D In the case of j+D > 128
(b) COM scan direction SC0 = 1 Scan start COM setting = j Display start row address setting = k Display line count setting = D In the case of j+D > 128
Figure 6. Relationship Between RAM Row Address Setting and COM Output
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Gray Scale Display In order to perform 4 gray scales (black, dark gray, light gray, and white) on a display, the ML9055A can set the lighting level pulse width of a segment drive waveform every frame for the 2-bit display data. This allows the ML9055A to support 2 modulation methods: pulse width modulation (PWM) and frame modulation (FRC), which in turn allows flexible setting according to the panel characteristics. For the frame cycle, which performs modulation, 3 frames or 4 frames can be selected by the set FRC field of FRC/PWM mode command. And 9, 12 or 15 can be selected as the number of PWM pulse width setting steps by the PWM1 and PWM0 fields, and the lighting pulse width of every frame of each gray scale is set by the set pulse width command. (Refer to Tables 7 and 8.) Example: In the setting (inversion display off) shown in Table 9, in pixels of the display RAM data 11, all the 3 frames output the segment drive waveform of pulse width 9/9 (driver voltage effective value maximum). Similarly, in pixels of the RAM data 10, the 1st and 2nd frames output the segment drive waveform of pulse width 9/9, and the 3rd frame outputs pulse width 0/9. In pixels of the RAM data 01, the 1st frame, 2nd frame and 3rd frame output the segment drive waveform of pulse width 9/9, 3/9 and 0/9, respectively. In pixels of the RAM data 00, all 3 frames output the segment drive waveform of pulse width 0/9 (driver voltage effective value minimum). Note: In order to avoid the occurrence of DC offset when using the 4-frame FRC, determine the pulse width setting values of each gray scale such that the sum of values of even number frames is equal to the sum of values of odd number frames.
Table 7. PWM Binary Setting for 4-frame FRC
RAM bit (1st Byte/ 2nd Byte) 11 10 01 00 PWM Binary Setting G/S Black Dark Gray Light Gray White 1st frame PWM (BA3-BA0) (DA3-DA0) (LA3-LA0) (WA3-WA0) 2nd frame PWM (BB3-BB0) (DB3-DB0) (LB3-LB0) (WB3-WB0) 3rd frame PWM (BC3-BC0) (DC3-DC0) (LC3-LC0) (WC3-WC0) 4th frame PWM (BD3-BD0) (DD3-DD0) (LD3-LD0) (WD3-WD0)
Table 8. PWM Binary Setting for 3-frame FRC
RAM bit (1st Byte/ 2nd Byte) 11 10 01 00 PWM Binary Setting G/S Black Dark Gray Light Gray White 1st frame PWM (BA3-BA0) (DA3-DA0) (LA3-LA0) (WA3-WA0) 2nd frame PWM (BB3-BB0) (DB3-DB0) (LB3-LB0) (WB3-WB0) 3rd frame PWM (BC3-BC0) (DC3-DC0) (LC3-LC0) (WC3-WC0)
Table 9. Example of PWM Binary Setting (3-frame FRC and 9-level PWM)
G/S Black Dark Gray Light Gray White 1st frame PWM 1001 1001 1001 0000 PWM Binary Setting 2nd frame PWM 1001 1001 0011 0000 3rd frame PWM 1001 0000 0000 0000
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Table 10. 9-Level PWM Settings
Decimal Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary Setting(*1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM Setting 0 1/9 2/9 3/9 4/9 5/9 6/9 7/9 8/9 1 0 0 0 0 0 0 Visual Appearance Lightest
Darkest
Set to lightest level.
(*1) The binary setting value can be any one of WA3-0, LA3-0, DA3-0, BA3-0, WB3-0, LB3-0, DB3-0, BB3-0, WC3-0, LC3-0, DC3-0, BC3-0, WD3-0, LD3-0, DD3-0, and BD3-0. Table 11. 12-Level PWM Settings
Decimal Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary Setting(*1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM Setting 0 1/12 2/12 3/12 4/12 5/12 6/12 7/12 8/12 9/12 10/12 11/12 1 0 0 0 Visual Appearance Lightest
Darkest Set to lightest level.
(*1) The binary setting value can be any one of WA3-0, LA3-0, DA3-0, BA3-0, WB3-0, LB3-0, DB3-0, BB3-0, WC3-0, LC3-0, DC3-0, BC3-0, WD3-0, LD3-0, DD3-0, and BD3-0.
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Table 12. 15-Level PWM Settings
Decimal Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary Setting(*1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM Setting 0 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 1 Visual Appearance Lightest
Darkest
(*1) Binary Setting Values are WA3-0, LA3-0, DA3-0, BA3-0, WB3-0, LB3-0, DB3-0, BB3-0, WC3-0, LC3-0, DC3-0, BC3-0, WD3-0, LD3-0, DD3-0, or BD3-0.
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Frame 1
Frame 2
1
2
3
4
5
...
127
128
1
2
3
4
5
...
127
128
V0 V1 V2 SEG V3 V4 VSS
1 8/9 3/9 2/9 1/9 V0
V2
Figure 7. Example of 9-Level PWM Segment Waveform
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Instruction Description Table 13. Instruction Set List x: Don't care
RS 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 BUSY D6 ON D5 RES D4 D3 1 0 Write data Read data 0 C3 1 0 1 P3 0 0 0 1 0 0 0 1 0 0 L4 L3 0 0 C4 C3 0 1 D4 D3 0 1 N4 N3 0 0 1 0 0 0 0 0 C4 C3 0 0 0 SC0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 D4 D3 1 0 0 1 WB0 WA3 0 1 WD0 WC3 0 1 LB0 LA3 0 1 LD0 LC3 0 1 DB0 DA3 0 1 DD0 DC3 0 1 BB0 BA3 0 1 BD0 BC3 1 x D2 1 D1 1 D0 0
0 0 1 1 1 0 0 0 x 0 x 0 D7 0 x 1 0 0 1 x 1 1 1 1 1 1 1 1 1 1 D7 1 1 WB3 1 WD3 1 LB3 1 LD3 1 DB3 1 DD3 1 BB3 1 BD3 1
0 0 0 1 1 0 0 1 L6 1 C6 1 D6 1 x 1 1 1 0 x 0 1 0 0 0 1 0 0 1 1 D6 0 0 WB2 0 WD2 0 LB2 0 LD2 0 DB2 0 DD2 0 BB2 0 BD2 1
0 0 1 1 1 1 1 0 L5 0 C5 0 D5 0 x 1 0 1 0 C5 1 0 1 1 1 1 1 1 1 1 D5 0 0 WB1 0 WD1 0 LB1 0 LD1 0 DB1 0 DD1 0 BB1 0 BD1 1
C2 C6 P2 0 1 R2 VC 0 L2 1 C2 0 D2 1 N2 1 BI2 1 0 C2 0 x 1 1 0 0 0 1 0 0 D2 FRC 0 WA2 0 WC2 0 LA2 0 LC2 1 DA2 1 DC2 1 BA2 1 BC2 x
C1 C5 P1 0 1 R1 VR x L1 x C1 x D1 x N1 0 BI1 BO1 0 C1 0 x 0 1 0 0 1 1 1 0 D1 PWM1 0 WA1 0 WC1 1 LA1 1 LC1 0 DA1 0 DC1 1 BA1 1 BC1 x
C0 C4 P0 0 0 R0 VF x L0 x C0 x D0 x N0 0 BI0 BO0 1 C0 S0 x E0 R0 1 1 1 DI0 0 0 D0 PWM0 0 WA0 1 WC0 0 LA0 1 LC0 0 DA0 1 DC0 0 BA0 1 BC0 x
Description Read internal status. Write display data. Read display data. Set column address (lower digits). Set column address (upper digits). Set page address. Set read modify write mode. Release read modify write mode. Set internal resistance ratio. Set power supply configuration. Set scan start COM. Set initial display line address. Set number of display lines. Set N-line inversion. Release N-line inversion. Set LCD bias ratio. Set voltage multiplication. Set contrast. Select ADC. Set COM scan direction. Light all dots. Reverse display on/off Set power save mode. Release power save mode. Start internal oscillator circuit. Display on/off. Reset Set display data length. (Used in 3-line interface only.) Set PWM/FRC mode. Set white pulse width, 1/2. Set white pulse width, 3/4 Gray scale register setting Set light gray pulse width, 1/2. Set light gray pulse width, 3/4 Set dark gray pulse width, 1/2 Set dark gray pulse width, 3/4 Set black pulse width, 1/2. Set black pulse width, 3/4
Test instruction for supplier exclusive use
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*
Read Internal Status
This command is only available in the parallel interface mode.
RS 0 R/W 1 D7 BUSY D6 ON D5 RES D4 1 D3 0 D2 1 D1 1 D0 0 Description Read internal status
0: Chip is idle. 1: Chip is executing an instruction. When this bit is "1", it indicates that this chip is executing an instruction. Normally it is not necessary to read the internal status because the command execution processing is completed in 1 system cycle time (tCYC). The reset operation by RESET pin does not pull this bit to "1". Refer to the RES bit described below. ON RES 0: Display is OFF. 1: Display is ON.
BUSY
0: Chip is in operating state. 1: Chip is executing the reset. This bit goes "1" during the execution of the reset either by RESET pin or by the reset command. Other commands cannot be executed while the reset is being executed. Since the reset execution processing is completed in 1 system cycle time, the next command can be input without reading this bit if wait-time of 1 system write cycle time (tCYC) is taken after the RESET pin is pulled to "H" or after having executed reset by the reset command. * Write Display Data The display data is written on to the display RAM at a location specified by the page address and column address. If using the 3-line serial interface, the set data display length command must be executed prior to inputting the display data. Column address automatically increments by one after every 2-byte data write operation, and returns to 0 after data is written to the last column address (7F). The page address does not increment even if the column address has returned to 0. The RAM must be written in 2 successive bytes because the 2-bit data for each pixel is written in 2 times. Refer to Figure 5 for the data structure. And about the write operation, refer to the Display Data Write Sequence.
RS 1 R/W 0 D7 D6 D5 D4 D3 Write data D2 D1 D0 Description Write display data.
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* Read Display Data Data is read from the display RAM at a location specified by the page address and column address. The column address increments automatically by one every 2-byte read operation, and returns to 0 after the data of last column address (7F) is read. The page address does not increment even if the column address has returned to 0. Dummy (1 byte) data reading is required once after the address setting, and the display data is read after having read that dummy data. For additional details on the read operation, refer to the Display Data Read Sequence. This command is available in the parallel interface mode only.
RS 1 R/W 1 D7 D6 D5 D4 D3 Read data D2 D1 D0 Description Read display data
*
Set Column Address
Specifies the column address (0 to 127) of the write/read destinations of display data. The column address increments automatically by one every 2 times a write display data command or a read display command is executed. It does not matter to execute the higher digit setting or the lower digit setting of a column address first. It is also possible to execute only either the higher digit setting or the lower digit setting of a column address.
RS 0 0 R/W 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 1 D3 C3 0 D2 C2 C6 D1 C1 C5 D0 C0 C4 Description Set column address (lower digits). Set column address (higher digits).
*
Set Page Address
Specifies the read/write destination page address (0 to 15) of the display data.
RS 0 R/W 0 D7 1 D6 0 D5 1 D4 1 D3 P3 D2 P2 D1 P1 D0 P0 Description Set page address
*
Set Read Modify Write Mode
In this mode, data is read from the display RAM at a location specified by the page address and column address, and the data is written to the same page address and column address. The column address does not increment after the 2-byte display data read operation, but increments by one after every 2-byte write operation. It is necessary to read a dummy data after the address setting. It is also necessary to read a dummy data after the 2-byte write operation. The display data cannot be read through the serial interface. For additional information on the read modify write operation, refer to the Read Modify Write Mode Sequence.
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 Description Set read modify write mode.
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*
Release Read Modify Write Mode
This command will release the read modify write mode.
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 Description Release read modify write mode.
*
Set Internal Resistance Ratio
3 bits are used to set the resistance ratio of internal resistors used in the voltage regulator. For details on the operation of the voltage regulator by the internal resistance ratio setting, refer to the "Voltage Regulator" section.
RS 0 R/W 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 R2 D1 R1 D0 R0 Description Set internal resistance ratio.
R2-R0 (0, 0, 0) (0, 0, 1) (0, 1, 0) (0, 1, 1) (1, 0, 0) (1, 0, 1) (1, 1, 0) (1, 1, 1) *
(1+Rb/Ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2
Set Power Supply Configuration
This command sets the operation of internal power supply for every block. VC = Voltage multiplier, VR = Voltage regulator, VF = Voltage follower. (0: Off, 1: On) Although the set power supply configuration command allows you to input commands for settings other than the combinations shown in Table 2, do not perform other settings as these would become a cause of the ML9055A malfunction.
RS 0 R/W 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 VC D1 VR D0 VF Description Set power supply configuration.
*
Set Scan Start COM (2-byte instruction)
This instruction specifies the COM number to start scanning. For details on the operation of the scan start COM setting, refer to Figure 6.
RS 0 0 R/W 0 0 D7 0 x D6 1 L6 D5 0 L5 D4 0 L4 D3 0 L3 D2 0 L2 D1 x L1 D0 x L0 Description Set scan start COM.
Note: Make sure to input the upper instruction before inputting the lower instruction.
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*
Set Initial Display Line Address (2-byte instruction)
This instruction is used to set the line address of display RAM that starts the display. The use of this instruction makes it possible to achieve a scroll in the vertical direction without changing the contents of the display data RAM. For details on the operation of the initial display line address setting, refer to Figure 6.
RS 0 0 R/W 0 0 D7 0 x D6 1 C6 D5 0 C5 D4 0 C4 D3 0 C3 D2 1 C2 D1 x C1 D0 x C0 Description Set initial display line address.
Note: Make sure to input the upper instruction before inputting the lower instruction. * Set Display Line Count (2-byte instruction) This instruction is used to set the duty ratio (1/16 to 1/128) of LCD display. The setting value determines the number of data lines displayed on the LCD display. The internal state does not change even by an invalid setting. For details on the operation of the display start line address setting, refer to Figure 6.
RS 0 0 R/W 0 0 D7 0 D7 D6 1 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 0 D2 D1 x D1 D0 x D0 Description Set the number of lines to be displayed.
Note: Make sure to input the upper instruction before inputting the lower instruction. D7 - D0 00000000
...
Duty Ratio Invalid Invalid 1/16 1/17 1/128 Invalid Invalid
... ... ...
00001111 00010000 00010001 10000000 10000001 11111111
... ...
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*
Set N-line Inversion (2-byte instruction)
This is a setting instruction to perform the N lines (3 to 33 lines) inversion drive for reducing the crosstalk noise.
RS 0 0 R/W 0 0 D7 0 x D6 1 x D5 0 x D4 0 N4 D3 1 N3 D2 1 N2 D1 x N1 D0 x N0 Description Set N-line inversion.
Note 1: In order to prevent the generation of DC bias and display irregularity, or unevenness on the display, the number of lines selected should not be set to a divisor that is twice the display duty ratio. Pay attention to this condition when using the N-lines inversion. Example: If the display duty ratio is 1/99, never set the N-line inversion to 3, 6, 9, 11, 18, 22, or 33 lines. Note 2: Make sure to input the upper instruction before inputting the lower instruction. N4 - N0 00000 00001
...
Setting number of inversion lines 0 lines (Frame inversion) 3 lines 32 lines 33 lines
... D7 1 D6 1 D5 1 D4 0
11110 11111 * Release N-line Inversion
This command releases the N-line inversion setting of driver (controller), causing frame inversion to occur.
RS 0 R/W 0 D3 0 D2 1 D1 0 D0 0 Description Release N-line inversion.
*
Set LCD Bias Ratio
Sets the LCD bias ratio (1/5 - 1/12).
RS 0 R/W 0 D7 0 D6 1 D5 0 D4 1 D3 0 D2 BI2 D1 BI1 D0 BI0 Description Set the LCD bias ratio.
BI2 0 0 0 0 1 1 1 1
BI1 0 0 1 1 0 0 1 1
BI0 0 1 0 1 0 1 0 1
Bias Ratio 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12
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*
Set Voltage Multiplication
This command is used to set the voltage multiplication. The available multiplications are: x3, x4, x5, and x6.
RS 0 R/W 0 D7 0 D6 1 D5 1 D4 0 D3 0 D2 1 D1 BO1 D0 BO0 Description Set voltage multiplication.
Note: Do not set the value exceeding the upper limit of voltage multiplications that are determined by the connection of external capacitors in the voltage multiplication configuration. BO1 0 0 1 1 * BO0 0 1 0 1 Voltage multiplication x3 x4 x5 x6
Set Contrast (2-byte instruction)
This instruction is used for fine tuning of the LCD drive voltage to adjust the display contrast. For details on the operation of contrast setting, refer to Table 4 and Figure 3.
RS 0 0 R/W 0 0 D7 1 x D6 0 x D5 0 C5 D4 0 C4 D3 0 C3 D2 0 C2 D1 0 C1 D0 1 C0 Description Set the contrast.
Note: Make sure to input the upper instruction before inputting the lower instruction. * Select ADC
Determines the correspondence between the column address of display data RAM and the segment driver (0: From SEG0 to SEG 127, 1: From SEG127 to SEG0) For details on the operation of ADC selection, refer to Figure 5.
RS 0 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 S0 Description Select ADC.
S0 0 1 *
Relationship between column address and segment output RAM column address i corresponds to SEGi. RAM column address i corresponds to SEG127-i.
Set COM Scan Direction
This instruction is used to set the COM (row) scan direction. (0: COM0 to COM127 direction, 1: COM127 to COM0 direction) For details on the operation of setting the COM scan direction, refer to Figure 6.
RS 0 R/W 0 D7 1 D6 1 D5 0 D4 0 D3 SC0 D2 x D1 x D0 x Description Set the COM scan direction.
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* Light All Dots Always outputs the lighting level regardless of the contents of the display data RAM, PWM setting, and reverse display on/off command. (0 : Normal display, 1: All dots light.)
RS 0 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 E0 Description Light all dots.
* Reverse Display On/Off Reverses the gray scale level relationship of each pixel without modifying the contents of display data RAM. (0: Normal, 1: Reverse image)
RS 0 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 0 RAM = "00" White Black D2 1 D1 1 D0 R0 Description Reverse display on/off RAM = "10" Dark gray Light gray RAM = "11" Black White
RAM contents Normal display: R0 = 0 Reverse display: R0 = 1
RAM = "01" Light gray Dark gray
* Set Power Save Mode Puts the driver (controller) into the power save mode as follows: Oscillator circuit: LCD power supply: COM/SEG output:
RS 0 R/W 0 D7 1
Off Off (Note) VSS
D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1 Description Set the power save mode.
Note: The LCD power supply consists of a voltage multiplier (VC), a voltage regulator (VR), and a voltage follower (VF). Among these, the circuits set to operating state by the set power supply configuration command are turned off in the power save mode. * Release Power Save Mode
Returns the driver (controller) from the power save mode. Circuits set to the operating state by the set supply configuration command only are turned on.
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 Description Release the power save mode.
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*
Start Internal Oscillator Circuit
This command activates the internal oscillator circuit. Note that since the oscillator circuit stops operation after the reset using the RESET pin, this instruction must be executed for initialization.
RS 0 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 1 Description Start internal oscillation circuit.
* Display On/Off Turns the display on and off without modifying the display data RAM content. (0: off, 1: on) This command has priority over Light All Dots and Reverse Display On/Off commands. Commands are accepted while the display is off, but the visual state of the display does not change.
RS 0 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 DI0 Description Display On/Off
*
Reset
Resets some functions of the driver/controller. See Reset Section below for more details.
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Description Reset
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*
Set Display Data Length (2-byte instruction)
This command is used in the 3-line serial interface mode (without RS signal). The specified number (1 to 256) of data bytes that continue after this set display data length command are processed as a display data. And a command that is input after the transmission of the display data is regarded as a command data. One pixel data consists of 2 bits. Set the display data length to even byte although odd byte setting also is possible. This is because writing from the 2nd byte of each pixel cannot be started. This command is ignored (NOOP) in the 4-line serial interface mode and 4-line parallel interface mode.
RS 0 0 R/W 0 0 D7 1 D7 D6 1 D6 D5 1 D5 D4 0 D4 D3 1 D3 D2 0 D2 D1 0 D1 D0 0 D0 Description Set the display data length.
Note: Make sure to input the upper instruction before inputting the lower instruction.
D7 0 0 0 : 1 1 1 D6 0 0 0 : 1 1 1 D5 0 0 0 : 1 1 1 D4 0 0 0 : 1 1 1 D3 0 0 0 : 1 1 1 D2 0 0 0 : 1 1 1 D1 0 0 1 : 0 1 1 D0 0 1 0 : 1 0 1 Display data length 1 2 3 : 254 255 256
*
Set FRC/PWM Mode
Sets the pulse width (PWM) and frame cycle (FRC) for gray-scale operation.
RS 0 R/W 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 FRC D1 D0 PWM1 PWM0 Description Set PWM and FRC mode
FRC 0: 4-frame 1: 3-frame
PWM1, PWM0 00: 9-level 01: 9-level 10: 12-level 11: 15-level
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*
Set Gray Scale Register (2-byte instruction)
This instruction is used for setting the PWM pulse width, frame-by-frame, corresponding to the 4-level gradation. For details on the operation of the register setting, refer to Tables 7 and 8.
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 1 WB3 1 WD3 1 LB3 1 LD3 1 DB3 1 DD3 1 BB3 1 BD3 D6 0 WB2 0 WD2 0 LB2 0 LD2 0 DB2 0 DD2 0 BB2 0 BD2 D5 0 WB1 0 WD1 0 LB1 0 LD1 0 DB1 0 DD1 0 BB1 0 BD1 D4 0 WB0 0 WD0 0 LB0 0 LD0 0 DB0 0 DD0 0 BB0 0 BD0 D3 1 WA3 1 WC3 1 LA3 1 LC3 1 DA3 1 DC3 1 BA3 1 BC3 D2 0 WA2 0 WC2 0 LA2 0 LC2 1 DA2 1 DC2 1 BA2 1 BC2 D1 0 WA1 0 WC1 1 LA1 1 LC1 0 DA1 0 DC1 1 BA1 1 BC1 D0 0 WA0 1 WC0 0 LA0 1 LC0 0 DA0 1 DC0 0 BA0 1 BC0 Description Set white pulse width, 1/2. Set white pulse width, 3/4. Set light gray pulse width, 1/2. Set light gray pulse width, 3/4. Set dark gray pulse width, 1/2. Set dark gray pulse width, 3/4. Set black pulse width, 1/2. Set black pulse width, 3/4.
WA3-WA0, LA3-LA0, DA3-DA0, BA3-BA0: First frame pulse width WB3-WB0, LB3-LB0, DB3-DB0, BB3-BB0: Second frame pulse width WC3-WC0, LC3-LC0, DC3-DC0, BC3-BC0: Third frame pulse width WD3-WD0, LD3-LD0, DD3-DD0, BD3-BD0: Fourth frame pulse width The 4th frame data is "don't care" in 3-frame FRC. Note: Make sure to input the upper instruction before inputting the lower instruction. * Test Instruction for Supplier Exclusive Use
RS 0 R/W 0 D7 1 D6 1 D5 1 D4 1 D3 x D2 x D1 x D0 x Description Test instruction for supplier exclusive use
This command is reserved for the test by the manufacturer - DO NOT USE!
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Reset Defaults Reset includes a hardware reset by RESET pin and software reset by the reset command. When the ML9055A is powered, the hardware reset by RESET pin must be performed prior to executing any other instructions. O: Initialization executed. : No change
Item Set column address (lower) Set column address (upper) Set page address Set internal resistance ratio Set power supply configuration Set scan start COM Set initial display line address Set number of display lines Set N-line inversion Set LCD bias ratio Set voltage multiplication Set contrast ADC select Set COM scan direction Light all dots Reverse display on/off Set power save mode Display on/off Set display data length Set FRC/PWM mode Set white pulse width, 1/2 Set white pulse width, 3/4 Set light gray pulse width, 1/2 Set light gray pulse width, 3/4 Set dark gray pulse width, 1/2 Set dark gray pulse width, 3/4 Set black pulse width, 1/2 Set black pulse width, 3/4 Oscillator circuit Parameter
(C3, C2, C1, C0) (C6, C5, C4) (P3, P2, P1, P0) (R2, R1, R0) (VC, VR, VF) (L6, L5, L4, L3, L2, L1, L0) (C6, C5, C4, C3, C2, C1, C0) (D7, D6, D5, D4, D3, D2, D1, D0) (N4, N3, N2, N1, N0) (BI2, BI1, BI0) (BO1, BO0) (C5, C4, C3, C2, C1, C0) S0 SC0 E0 R0 DI0 (D7, D6, D5, D4, D3, D2, D1, D0) (FRC, PWM1, PWM0) (WB3, WB2, WB1, WB0, WA3, WA2, WA1, WA0) (WD3, WD2, WD1, WD0, WC3, WC2, WC1, WC0) (LB3, LB2, LB1, LB0, LA3, LA2, LA1, LA0) (LD3, LD2, LD1, LD0, LC3, LC2, LC1, LC0) (DB3, DB2, DB1, DB0, DA3, DA2, DA1, DA0) (DD3, DD2, DD1, DD0, DC3, DC2, DC1, DC0) (BB3, BB2, BB1, BB0, BA3, BA2, BA1, BA0) (BD3, BD2, BD1, BD0, BC3, BC2, BC1, BC0)
Initial value after reset
(0, 0, 0, 0) (0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) (0, 0, 0, 0, 0, 0, 0) (0, 0, 0, 0, 0, 0, 0) (1, 0, 0, 0, 0, 0, 0, 0) (0, 0, 0, 0, 0) (1, 1, 1) (0, 0) (1, 0, 0, 0, 0, 0) 0 0 0 0
Hardware
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
Software
O O O O O O O O O O O O O O O O
Remarks
2.3 times Voltage multiplicatier, regulator, and VF amp. are all off.
128 lines Frame inversion 1/12 bias 3 times
32
RAM address i corresponds to SEGi.
COM0COM127
Normal display Normal display
Release
0 (0, 0, 0, 0, 0, 0, 0, 0) (0, 0, 0) (0, 0, 0, 0, 0, 0, 0, 0) (0, 0, 0, 0, 0, 0, 0, 0) (0, 0, 0, 0, 0, 0, 0, 0) (0, 0, 0, 0, 0, 0, 0, 0) (1, 1, 1, 1, 1, 1, 1, 1) (1, 1, 1, 1, 1, 1, 1, 1) (1, 1, 1, 1, 1, 1, 1, 1) (1, 1, 1, 1, 1, 1, 1, 1) OFF
Off 1 byte 4-frame, 9-level
Internal oscillator circuit stops operation.
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OPERATING SEQUENCE
Power-on Sequence in Using the Built-in Power Supply Circuits
Start of Initialization
Power ON VDD (*1) (Hold the RESET pin = "L".) Wait for VDD to stabilize.
RESET pin = "H"
User application set-up -Set the number of display lines. -Select ADC. -Set COM scan direction. -Set initial display line. -Set N-line inversion. (*2) -Set PWM and FRC. -Set gray scale register. User LCD power supply set-up -Start internal oscillator circuit. -Set voltage multiplication. -Set internal resistance ratio. (*3) -Set contrast. -Set LCD bias ratio. Set power supply configuration. Wait for LCD power supply to stabilize. (*4) Input display data. (*1): Apply VCI also simultaneously with VDD. (*2): Only when line inversion is used. When using frame inversion, either release N-line inversion or specify 0 lines. (*3): Only when using the internal resistors. (*4): The stabilizing time primarily depends on factors such as the voltage multiplier setting, the internal resistance ratio, and the external capacitors.
Display ON End of Initialization
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Power-on Sequence in Using an External Power Supply Circuit
Start of Initialization
Power ON VDD (*1) (Hold the RESET pin = "L".) Wait for VDD to stabilize.
RESET pin = "H"
Set power save mode.
User application set-up -Set the number of display lines. -Select ADC. -Set COM scan direction. -Set scan start COM. -Set initial display line. -Set N-line inversion. (*2) -Set PWM and FRC. -Set gray scale register.
User LCD power supply set-up -Start internal oscillator circuit. -Set internal resistance ratio. (*3) -Set contrast. -Set LCD bias ratio. (*4) -Set power supply configuration. (*1): Apply VCI also simultaneously with VDD. (*2): Only when line inversion is used. When using the frame inversion, either release N-line inversion or specify 0 lines. (*3): Only when using the internal resistors. (*4): Only when using the voltage follower. (*5): Input sequentially external power supplies from the one with higher potential. (*6): The stabilizing time primarily depends on factors such as the internal resistance ratio, and the external capacitors.
Release the power save mode. Power ON the external power supply. (*5) Wait for LCD power supply to stabilize. (*6) Input display data. Display ON
End of Initialization
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Power off Sequence in Using a Built-in Power Supply
Start of Power OFF
Set power save mode.
Power OFF VDD
End of Power OFF
Power off Sequence in Using an External Power Supply
Start of Power OFF
Power OFF external power supply.
Set power save mode.
Power OFF VDD.
End of Power OFF
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Start and End of Power Save Sequence in Using a Built-in Power Supply
Start of Power Save
Display OFF
Set power save mode.
Power save mode Oscillator circuit: OFF LCD Power Supply: OFF COM/SEG Outputs: VSS
Release powe save mode.
Wait for LCD power supply level to stabilize. (*1)
Display ON
(*1) The stabilized time depends on the voltage multiplier setting, the internal resistance ratio, the external capacitors, and so on.
End of Power Save
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Start and End of Power Save Sequence in Using an External Power Supply
Start of Power Save Mode
Display OFF
External power supply OFF
Set power save mode.
Power save mode Oscillator circuit: LCD power supply: COM/SEG output:
OFF OFF (*1) VSS
Release power save mode. (*2)
Power on the external power supply.
(*1): Turns off the circuits set to operating state by the set power supply configuration instruction. (*2): The LCD power supplies set to the operating state only are turned on by the set power supply configuration instruction. (*3): The stabilizing time primarily depends on factors such as the voltage multiplier setting, the internal resistance ratio, and the external capacitors.
Wait for LCD power supply level to stabilize. (*3)
Display ON
End of Power Save
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Partial Display Change Sequence in Using a Built-in Power Supply
Start of Partial Display Change
Display OFF
Set power save mode.
User application set-up -Set display lines. -Set scan start COM. -Set initial display line.
User LCD power set-up -Start internal oscillator circuit. -Set voltage multiplication. -Set internal resistance ratio. -Set contrast. -Set LCD bias ratio.
Release power save mode.
Wait for LCD power supply level to stabilize. (*1) Display ON
End of Partial Display Change
(*1) The stabilized time depends on the voltage multiplier setting, the internal resistance ratio, the external capacitors, and so on.
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Partial Display Chang Sequence in Using an External Power Supply
Start of Partial Display Change
Display OFF
External power supply OFF
Set power save mode.
User application set-up -Set the number of display lines. -Set scan start COM. -Set initial display line.
User LCD power supply set-up -Start internal oscillator circuit. -Set voltage multiplication. (*1) -Set internal resistance ratio. (*2) -Set contrast. (*3) -Set LCD bias ratio. (*4)
Release power save mode. (*1). Only when using the built-in voltage multiplier. (*2). Only when using the internal resistors. (*3). Only when using the built-in voltage regulator. (*4). Only when using the built-in voltage follower. (*5). The stabilizing time primarily depends on factors such as the voltage multiplier, the internal resistance ratio, and the external capacitors.
External power supply ON
Wait for LCD power supply to stabilize. (*5) Display ON
End of Partial Display Change
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Display Data Write Sequence
Start of Display Data Write
Set page address.
Set column address.
Write 1st byte of data.
Write 2nd byte of data.
Continue to write the display data?
Yes
No
End of Display Data Write
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Display Data Read Sequence
Start of Display Data Read
Set page address.
Set column address.
Read dummy data. (Note 1)
Read 1st byte of data.
Read 2nd byte of data.
Continue to read the display data? No
Yes
End of Display Data Read
Note 1: Although the display RAM data is of 2 bytes, the dummy data is read once (1 byte) only. Note 2: The trace impedance (specially, the VDD, VSS, VCI impedance and the data bus trace capacitance etc.,) between this chip and circuit board should be designed as low as possible. Factors such as not sufficiently low trace impedance, LCD panel of large size, and higher trace impedance of the microcomputer interface, would become a cause of the ML9055A malfunction. In such a situation, use the microcomputer interface not for reading, but for writing only to reduce the power supply noise.
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Read Modify Write Sequence
Start of Read Modify Write
Set page address.
Set column address.
Set read modify write.
Read dummy data. (Note 1)
Read 1st byte of data.
Read 2nd byte of data.
Write 1st byte of data.
Write 2nd byte of data.
Continue read modify write? No Release read modify write.
Yes
End of Read Modify Write
Note 1: Although the display RAM data is of 2 bytes, the dummy data is read once (1 byte) only. Note 2: In the case of the read modify write operation, it is necessary to read dummy data for every read operation. Note 3: The trace impedance (specially, the VDD, VSS, VCI impedance and the data bus trace capacitance etc.,) between this chip and circuit board should be designed as low as possible. Factors such as not sufficiently low trace impedance, LCD panel of large size, and high trace impedance of the microcomputer interface, would become a cause of the ML9055A malfunction. In such a situation, use the microcomputer interface not for reading, but for writing only to reduce the power supply noise.
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PAD CONFIGURATION
Pad Layout Chip Size: 9.28mm x 3.95 mm Chip Thickness: 62515 m Bump Size (1): 70 x 70 m (PAD No. 1-100) Bump Size (2): 70 x 37 m (PAD No. 101-369)
318 319 (Gold Bump Top View)
Y
152 151
X
369 101 1
100
Pad Coordinates
Pad No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Pad Name
DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY-B DUMMY-B VDD TEST2 VSS PS0 VDD PS1 VSS CS RESET VDD RS R/W (WR) VSS E (RD) VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD
X (m)
-4270 -4185 -4100 -4015 -3930 -3845 -3760 -3675 -3590 -3505 -3420 -3335 -3250 -3165 -3080 -2995 -2910 -2825 -2740 -2655 -2570 -2485 -2400 -2315 -2230 -2145 -2060 -1975 -1890 -1805 -1720 -1635 -1550
Y (m)
-1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843
Pad No.
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
Pad Name
VDD VDD VDD VDD VDD VCI VCI VSS VSS VSS VSS VSS VSS VSS VOUT VOUT C5+ C5+ C3+ C3+ C1- C1- C1+ C1+ C2+ C2+ C2- C2- C4+ C4+ VDD VDD REF
X (m)
-1465 -1380 -1295 -1210 -1125 -1040 -955 -870 -785 -700 -615 -530 -445 -360 -275 -190 -105 -20 65 150 235 320 405 490 575 660 745 830 915 1000 1085 1170 1255
Y (m)
-1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843
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Pad No.
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Pad Name
VSS VEXT VDD INTRS VSS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 VR VR VSS VSS VDD TEST1 DUMMY-B DUMMY-B DUMMY-B DUMMY-B DUMMY-B DUMMY-B DUMMY-B DUMMY-B DUMMY-B DUMMY-B DUMMY DUMMY DUMMY DUMMY COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39
X (m)
1340 1425 1510 1595 1680 1765 1850 1935 2020 2105 2190 2275 2360 2445 2530 2615 2700 2785 2870 2955 3040 3125 3210 3295 3380 3465 3550 3635 3720 3805 3890 3975 4060 4145 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509
Y (m)
-1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1843 -1627 -1575 -1523 -1471 -1419 -1367 -1315 -1263 -1211 -1159 -1107 -1055 -1003 -951 -899 -847 -795 -743 -691 -639 -587 -535 -483 -431 -379 -327 -275
Pad No.
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188
Pad Name
COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 DUMMY DUMMY DUMMY COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 DUMMY DUMMY SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
X (m)
4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4509 4342 4290 4238 4186 4134 4082 4030 3978 3926 3874 3822 3770 3718 3666 3614 3562 3510 3458 3354 3302 3250 3198 3146 3094 3042 2990 2938 2886 2834 2782 2730 2678 2626 2574 2522 2470 2418
Y (m)
-223 -171 -119 -67 -15 37 89 141 193 245 297 349 401 453 505 557 609 661 713 765 817 869 921 1619 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843
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Pad No.
189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249
Pad Name
SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77
X (m)
2366 2314 2262 2210 2158 2106 2054 2002 1950 1898 1846 1794 1742 1690 1638 1586 1534 1482 1430 1378 1326 1274 1222 1170 1118 1066 1014 962 910 858 806 754 702 650 598 546 494 442 390 338 286 234 182 130 78 26 -26 -78 -130 -182 -234 -286 -338 -390 -442 -494 -546 -598 -650 -702 -754
Y (m)
1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843
Pad No.
250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310
Pad Name
SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 DUMMY COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73
X (m)
-806 -858 -910 -962 -1014 -1066 -1118 -1170 -1222 -1274 -1326 -1378 -1430 -1482 -1534 -1586 -1638 -1690 -1742 -1794 -1846 -1898 -1950 -2002 -2054 -2106 -2158 -2210 -2262 -2314 -2366 -2418 -2470 -2522 -2574 -2626 -2678 -2730 -2782 -2834 -2886 -2938 -2990 -3042 -3094 -3146 -3198 -3250 -3302 -3354 -3406 -3458 -3510 -3562 -3614 -3666 -3718 -3770 -3822 -3874 -3926
Y (m)
1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843 1843
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PEDL9055A-02-01
OKI Semiconductor
ML9055A-02
Pad No.
311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340
Pad Name
COM74 COM75 COM76 COM77 COM78 COM79 DUMMY DUMMY DUMMY COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100
X (m)
-3978 -4030 -4082 -4134 -4186 -4238 -4290 -4342 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509
Y (m)
1843 1843 1843 1843 1843 1843 1843 1843 1619 921 869 817 765 713 661 609 557 505 453 401 349 297 245 193 141 89 37 -15 -67 -119
Pad No.
341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369
Pad Name
COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 DUMMY DUMMY
X (m)
-4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509 -4509
Y (m)
-171 -223 -275 -327 -379 -431 -483 -535 -587 -639 -691 -743 -795 -847 -899 -951 -1003 -1055 -1107 -1159 -1211 -1263 -1315 -1367 -1419 -1471 -1523 -1575 -1627
(Note): Leave DUMMY-B pads open. Do not run trace or do not share them with other DUMMY pads and DUMMY-B pads.
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PEDL9055A-02-01
OKI Semiconductor
ML9055A-02
ML9055A ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
A Y
.....................................................................................................
(0,0)
X B
Alignment Mark A B
X Coordinate (m)
-4509
Y Coordinate (m) 1843
-1843
4509
Alignment Mark Layer Bump layers Alignment Mark Specification
Symbol Parameter Alignment Mark Width Alignment Mark Size Minimum distance between Mark and Adjacent Pad Bump Mark -- -- Mark A Mark B Size (m) 43 98 85.8 134.7
a b c
b
c
Bump
a b
a c
Bump
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PEDL9055A-02-01
OKI Semiconductor
ML9055A-02
ML9055ADVX GOLD BUMP SPECIFICATION
(Low hardness product) Gold Bump Specification
(Unit: m) Symbol A B C D E F G H I J K L M N Parameter Bump Pitch (Min. Section: Output Section) Bump Size (Output Section: Pitch Direction) Bump Size (Output Section: Depth Direction)
Bump-to-Bump Distance (Output Section: Pitch Direction)
MIN. 52 32 65 10 65 65 10 93 38 --- 10 --- --- 18 30
TYP. ---
MAX. --- 42 75 20 75 75 20 103 48 2 20 3 5 --- 80
37
70 15 70 70
Bump Size (Input Section: Pitch Direction) Bump Size (Input Section: Depth Direction)
Bump-to-Bump Distance (Input Section: Pitch Direction)
15
98 43 --- 15 --- --- --- ---
Bump Size ("L" Alignment Mark: Length) Bump Size ("L" Alignment Mark: W idth) Tolerance between Pad and Bump Centers Bump Height Bump Height Dispersion Inside Chip (Range) Bump Edge Height Shear Strength (g) Bump Hardness (Hv: 25 g load)
Chip Thickness: 625 15 m Chip Size: 9.28 mm x 3.95 mm
Top View and Cross Section View
L C*F "L" Alignment Mark I H Cross Section View A B*E
D*G Input and Output Sections
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K
PEDL9055A-02-01
OKI Semiconductor
ML9055A-02
REVISION HISTORY
Document No.
PEDL9055A-02-01
Date
Jul. 26, 2002
Page Previous Current Edition Edition
- -
Description
Preliminary first edition
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PEDL9055A-02-01
OKI Semiconductor
ML9055A-02
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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